`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/09 08:28:44
// Design Name: 
// Module Name: counter
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module counter(
    input clk_i,
    input rst,
    output out
    );
    
    parameter cnt_max = 10000000;
    parameter cnt_half = 5000000;
    reg [26:0] cnt = 27'b0;
    wire rst_n = ~rst;
    
    always@ (posedge clk_i or posedge rst_n) begin
        if (rst_n == 1'b1) begin
            cnt <= 27'h0;
        end else begin
            cnt <= (cnt>=cnt_max) ? 20'h0 : (cnt+27'h1);
        end
    end
    
    assign out = (cnt>=cnt_half) && rst;
endmodule
